The capacity and the density of semiconductor integrated memory circuits have been greatly increased; however, the data processing speed of semiconductor integrated memory circuits has not been able to keep pace with the increases in system processing speed. In a conventional semiconductor integrated circuit, when a column address strobe signal CAS is at a precharge level the data output is at a high impedance state. To achieve high speed data access, efforts have been made to reduce the time required for maintaining the high impedance state during data output. There has been proposed a fast page mode. If the fast page mode operates more rapidly in the semiconductor integrated circuit, the time for which effective data is outputted and maintained is also relatively shortened. In such an arrangement, a high impedance state may occur between first effective data and second effective data when sampling the effective data in a system, and an error may occur due to the reduction of time in which the effective data is output.
FIG. 1 is a timing diagram showing a conventional data access operation in a typical dynamic random access memory (DRAM) product, such as model KMM591000AN of the Samsung Electronics company. A row address is latched at the falling edge of a row address strobe signal RAS, and a word line corresponding to the row address is selected. Data stored in memory cells having gates connected to the selected word line is output to each corresponding bit line and is sensed by a bit line sense amplifier. Upon the completion of the sensing operation, a data received signal .phi.RCD is enabled.
Thereafter, desired data is selected by a column address latched at the falling edge of a column address strobe signal CAS. The selected data is transmitted to a data input/output line via a column gate. The desired data is then amplified by an input/output sense amplifier formed on the data input/output line and output to a data output buffer. The data in the data input/output buffer is provided to the exterior of the chip under the control of a data output buffer enable signal .phi.TRST. As illustrated in FIG. 1, when the column address strobe signal CAS is at a precharge state (the logic high state), the data output Dout goes to a high impedance state. In the next cycle, cell data selected by a new column address COL2 is outputted to the exterior of a chip through the same operation described above, and the operation course occurring after data output is the same as discussed above.
As illustrated in FIG. 1, the data output Dout is at a high impedance state each time the column address strobe signal CAS goes to a precharge state. As a result, the time for maintaining the output state of effective data must be limited to the active interval of the column address strobe signal CAS. If the active interval of the column address strobe signal CAS is shortened the time for maintaining the output state of the effective data is also shortened. In the fast page mode previously discussed, the time for maintaining the output state of the effective data is severely reduced. Therefore, it is difficult to ensure that a system will achieve a safe sampling of the desired data.